Parallel execution of instructions through execution units, or pipelines, is known in the art to benefit EPIC processors. Certain of these processors utilize redundant processing cores on a common die. It is also known in the art to group execution units as a “cluster” to process instructions as a “bundle.” One such bundle has three instructions; each cluster operates to process one bundle, or more, of instructions.
Certain EPIC processors utilize heuristics to suggest an answer to a program inquiry. By way of example, a processor's internal logic and software may monitor program cache misses during runtime activity and then apply a heuristic to correctly set prefetch hints.
VLSI designers and software engineers expend significant efforts optimizing hardware and software designs of EPIC processors, and their guiding heuristics, in order to accelerate the processing of instructions and/or bundled instructions through the pipelines. Further advancements are sought to provide faster and more stable processors.
The invention seeks to advance the state of the art in processing architectures by providing methods and systems for processing instructions through execution units. One feature of the invention is to provide a processor with dual cores for optimizing the processing of bundled instructions. Several other features of the invention are apparent within the description that follows.